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PRELIMINARY
LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR
ICS873991-147
GENERAL DESCRIPTION
The ICS873991-147 is a low voltage, low skew, 3.3V IC S LVPECL or ECL Clock Generator and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS873991-147 has two selectable clock inputs. The PCLK, nPCLK pair can accept an LVPECL input and the REF_CLK pin can accept a LVCMOS or LVTTL input. This device has a fully integrated PLL along with frequency configurable outputs. An external feedback input and output regenerates clocks with "zero delay". The four independent banks of outputs each have their own output dividers, which allow the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The output frequency range is 25MHz to 500MHz and the input frequency range is 6.25MHz to 125MHz. The PLL_SEL input can be used to bypass the PLL for test and system debug purposes. In bypass mode, the input clock is routed around the PLL and into the internal output dividers. The ICS873991-147 also has a SYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs for coincident rising edges and signals a pulse per the timing diagrams in this data sheet. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of each other. Example Applications: 1. Line Card Multiplier: Multiply 19.44MHz from a back-plane to 77.76MHz on the line card ASIC and Serdes. 2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies from a reference clock to multiple processing units on an embedded system.
FEATURES
* Fourteen differential 3.3V LVPECL/ECL outputs * Selectable differential LVPECL or REF_CLK inputs * PCLK, nPCLK can accept the following input levels: LVPECL, CML, SSTL * REF_CLK accepts the following input levels: LVCMOS, LVTTL * Input clock frequency range: 6.25MHz to 125MHz * Maximum output frequency: 500MHz * VCO range: 200MHz to 1GHz * Output skew: 70ps (typical) * Cycle-to-cyle jitter: 35ps (typical) * LVPECL mode operating voltage supply range: VCC = 3.135V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -3.135V * 0C to 70C ambient operating temperature * Available in lead-free (RoHS 6) package * Industrial temperature available upon request
PIN ASSIGNMENT
FSEL0 FSEL1 FSEL2
nQB3 QB3 VCCO nQA0 QA0 nQA1 QA1 nQA2 QA2 nQA3 QA3 SYNC_SEL VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27 40 41 42 43 44 45 46 47 48 49 50 51 52 1
VEE
FSEL3
nQC2
nQB2
nQB1
nQB0
VCCO
QC2
QB2
QB1
QB0
26 25 24 23
QC1 nQC1 QC0 nQC0 VCCO QD1 nQD1 QD0 nQD0 VCCO QFB nQFB VCCA
ICS873991-147
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
22 21 20 19 18 17 16 15 14
23
MR PLL_EN
456
REF_SEL FSEL_FB2 FSEL_FB1
7 8 9 10 11 12 13
FSEL_FB0 REF_CLK nEXT_FB EXT_FB PCLK nPCLK VCC
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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BLOCK DIAGRAM
VCO_SEL Pulldown PLL_EN Pulldown REF_SEL Pulldown REF_CLK Pulldown nPCLK PCLK QA0 nQA0 QA1 nQA1 QA2
PHASE DETECTOR LPF
VCO
nQA2 QA3 nQA3 QB0 nQB0 QB1 nQB1
EXT_FB nEXT_FB MR Pulldown
FREQUENCY GENERATOR
FSEL_0:3 Pulldown
QB2 nQB2 QB3 nQB3 QC0
SYNC
FSEL_FB0:2 Pulldown
nQC0 QC1 nQC1 QC2 nQC2 QD0 nQD0 QD1 nQD1 QFB nQFB
SYNC_SEL Pulldown
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TABLE 1. PIN DESCRIPTIONS
Number 1 2 Name VEE MR Power Input Type Description Negative supply pin. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inver ted outputs Pulldown (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH, Pulldown PLL is in bypass mode. LVCMOS/LVTTL interface levels. Selects between the different reference inputs as the PLL reference Pulldown source. When logic LOW, selects PCLK/nPCLK. When logic HIGH, selects REF_CLK. LVCMOS/LVTTL interface levels. Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels. Pulldown Reference clock input. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Core supply pin. Pulldown Non-inver ting external feedback input. Pullup/ Inver ting external feedback input. VCC/2 default when left floating. Pulldown Analog supply pin. Differential feedback output pair. LVPECL Interface levels. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. SYNC output select pin. When LOW, the SYNC otuput follows the Pulldown timing diagram (page 5). When HIGH, QD output follows QC output LVCMOS/LVTTL interface levels.. Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17, 22, 30, 42 18, 19 20, 21 23, 24 25, 26 27 33 36 39 28, 29 31, 32 34, 35 37, 38 40, 41 43, 44 45, 46 47, 48 49, 50 51 52
PLL_EN REF_SEL FSEL_FB2 FSEL_FB1 FSEL_FB0 REF_CLK PCLK nPCLK VCC EXT_FB nEXT_FB VCCA nQFB QFB VCCO nQD0, QD0 nQC0, QC0
Input Input
Input Input Input Input Power Input Input Power Output Power Output Output
nQD1, QD1 Output nQC1, QC1 Output FSEL3 FSEL2 Input FSEL1 FSEL0 nQC2, QC2 Output nQB0, QB0 nQB1, QB1 nQB2, QB2 nQB3, QB3 nQA0, QA0 nQA1, QA1 nQA2, QA2 nQA3, QA3 SYNC_SEL VCO_SEL Output Output Output Output Output Output Output Output Input Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLup Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 3A. SELECT PIN FUNCTION TABLE
Inputs FSEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QAx /2 /2 /2 /2 /2 /2 /2 /2 /2 /2 /4 /4 /4 /6 /6 /8 Outputs QBx /2 /2 /4 /2 /6 /4 /4 /6 /2 /8 /4 /6 /6 /6 /8 /8 QCx /2 /4 /4 /6 /6 /6 /8 /8 /8 /8 /6 /6 /8 /8 /8 /8
TABLE 3B. FEEDBACK CONTROL FUNCTION TABLE
Inputs FSEL_FB2 0 0 0 0 1 1 1 1 FSEL_FB1 0 0 1 1 0 0 1 1 FSEL_FB0 0 1 0 1 0 1 0 1 Outputs QFB /2 /4 /6 /8 /8 /16 /24 /32
TABLE 3C. INPUT CONTROL FUNCTION TABLE
Control Input Pin PLL_EN VCO_SEL REF_SEL MR SYNC_SEL Logic 0 Enables PLL fVCO Selects PCLK/nPCLK --Selects outputs Logic 1 Bypasses PLL fVCO/2 Selects REF_CLK Resets outputs Match QC Outputs
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1:1 Mode
QA QC SYNC (QD)
2:1 Mode
QA QC SYNC (QD)
3:1 Mode
QA QC SYNC (QD)
3:2 Mode
QA QC SYNC (QD)
4:3 Mode
QA QC SYNC (QD)
FIGURE 1. TIMING DIAGRAMS
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5 V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi-mum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 63.7C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C TO 70C
Symbol VCC VCCA VCCO ICC ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 150 15 95 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C TO 70C
Symbol Parameter PLL_EN, VCO_SEL, REF_SEL, SYNC_SEL, FSEL_FB0:FSEL_FB2, FSEL0:FSEL3, MR REF_CLK PLL_EN, VCO_SEL, REF_SEL, SYNC_SEL, FSEL_FB0:FSEL_FB2, FSEL0:FSEL3, MR REF_CLK VCC = VIN = 3.465V VIN = 0V, VCC = 3.465V -5 Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VCC + 0.3 VCC + 0.3 0.8 1.3 150 Units V V V V A A
VIH
Input High Voltage
VIL
Input Low Voltage
IIH IIL
Input High Current Input Low Current
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, VEE = 0V, TA = 0C TO 70C
Symbol Parameter IIH IIL VPP VCMR VOH VOL Input High Current Input Low Current PCLK nPCLK PCLK nPCLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.3 VEE + 1.5 VCC - 1.4 VCC - 2.0 0.6 1 VCC VCC - 0.9 VCC - 1.7 1 Minimum Typical Maximum 150 5 Units A A A A V V V V V
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1 Output High Voltage; NOTE 2 Output Low Voltage; NOTE 2
VSWING Peak-to-Peak Output Voltage Swing NOTE 1: Common mode voltage is defined as VIH. NOTE 2: Outputs terminated with 50 to VCCO - 2V. .
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TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol t R / tR Parameter Input Rise/Fall Time REF_CLK Feedback / 6 Feedback / 8 Reference Frequency VCO_SEL = 0 Feedback / 16 Feedback / 24 Feedback / 32 fREF Reference Frequency VCO_SEL = 1 Feedback / 4 Feedback / 6 Feedback / 8 Feedback / 16 Feedback / 24 Feedback / 32 fREFDC Reference Input Duty Cycle 66.66 50 25 16.66 12.5 50 33.33 25 12.5 8.33 6.25 25 Test Conditions Minimum Typical Maximum 3 166.67 125 62.5 41.67 31.25 100 66.66 50 25 16.66 12.5 75 Units ns MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz %
NOTE: These parameters are guaranteed by design, but are not tested in production.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0C TO 70C
Symbol Parameter QA, QB, QC fMAX t(O) tsk(o) t sk(w) tjit(cc) f VCO t LOCK tR / tF Output Frequency QD SYNC_SEL = 1 SYNC_SEL = 0 170 70 TBD 35 PLL_SEL = 0 PLL_SEL = 1 20% to 80% 0.4 200 0.5 1. 0 480 10 QD; NOTE 1 Static Phase Offset; PCLK, nPCLK NOTE 2, 3 Output Skew; NOTE 4, 5 Multiple Frequency Skew; NOTE 5, 6 Cycle-to-Cycle Jitter; NOTE 5 PLL VCO Lock Range; NOTE 7 PLL Lock Time Output Rise/Fall Time Test Conditions Minimum Typical Maximum 500 400 200 Units MHz MH z MHz ps ps ps ps GHz MH z ms ns %
odc Output Duty Cycle 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: SYNC output (QD when SYNC_SEL = 0) operation guaranteed to 800MHz maximum VCO frequency. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Static phase offset is specified for an input frequency of 50MHz with feedback in /8. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VCCO/2. NOTE 7: When VCO_SEL = 0, the PLL will be unstable with feedback configurations of /2, /4 and some /6. When VCO_SEL = 1, the PLL will be unstable with a feedback configuration of /2.
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PARAMETER MEASUREMENT INFORMATION
2V
VCC, VCCA, VCCO
Qx
SCOPE
VCC
LVPECL
VEE
nQx
nPCLK V PCLK
PP
Cross Points
V
CMR
-1.3V -0.165V
VEE
OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
DIFFERENTIAL INPUT LEVELS
nQFB, nQAx:nQDx QFB, QAx:QDx
tcycle n
tsk(o)
tjit(cc) = tcycle n - tcycle n+1 1000 Cycles
OUTPUT SKEW
nPCLK PCLK nQFB, nQAx:nQDx QFB, QAx:QDx
VOH VOL
CYCLE-TO-CYCLE JITTER
nQxx Qxx
VOH VOL
nQyy Qyy
tsk()
t(O)
STATIC PHASE OFFSET
MULTIPLE FREQUENCY SKEW
nQFB, nQAx:nQDx 80% 80% VSW I N G QFB, QAx:QDx
t PW
t
PERIOD
Clock Outputs
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tcycle n+1
x 100%
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APPLICATIONS INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS873991-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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LVPECL CLOCK INPUT INTERFACE
The PCLK/nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and V CMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R2 50
3.3V Zo = 50 Ohm
3.3V
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100 - 200 R6 100 - 200 Zo = 50 Ohm C2 3.3V 3.3V LVPECL Zo = 50 Ohm C1
3.3V 3.3V R3 84 R4 84 PCLK
R4 125
nPCLK
HiPerClockS PCLK/nPCLK
R1 125
R2 125
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V 3.3V 3.3V Zo = 50 Ohm LVDS R5 100 Zo = 50 Ohm R1 1K R2 1K C1 R3 1K R4 1K PCLK C2 nPCLK HiPerClockS PCL K/n PC LK
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
PCLK/nPCLK INPUTS For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS873991-147. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS873991-147 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.75mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 14 * 30mW = 420mW
Total Power_MAX (3.465V, with all outputs switching) = 519.75mW + 420mW = 939.75mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 55.5C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.940W * 55.5C/W = 122.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE JA FOR 52-PIN LQFP FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 63.7C/W
1
55.5C/W
2.5
52.4C/W
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 0.9V (VCCO_MAX - VOH_MAX) = 0.9V
*
For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) =
L L
[(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L L
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE
FOR
52 LEAD LQFP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 63.7C/W
1
55.5C/W
2.5
52.4C/W
TRANSISTOR COUNT
The transistor count for ICS873991-147 is: 5969
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PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.22 0.09 BCC MINIMUM NOMINAL 52 --1.40 0.32 -12.00 BASIC 10.00 BASIC 7.80 Ref. 12.00 BASIC 10.00 BASIC 7.80 Ref. 0.65 BASIC ---0.75 7 0.10 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
IDT TM / ICSTM LVPECL/ECL CLOCK GENERATOR
15
ICS873991AY-147 REV. A AUGUST 10, 2007
ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number 873991AY-147LF 873991AY-147LFT Marking ICS873991A147L ICS873991A147L Package 52 Lead "Lead-Free" LQFP 52 Lead "Lead-Free" LQFP Shipping Packaging tray 500 tape & reel Temperature 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM LVPECL/ECL CLOCK GENERATOR
16
ICS873991AY-147 REV. A AUGUST 10, 2007
ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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